This invention is directed to programmable logic devices (“PLD”). More particularly, this invention is related to communications between a memory block and other portions of the PLD or communications between a memory block on a PLD and other electronic devices.
A programmable logic device (“PLD”) is a programmable integrated circuit that allows a user, using software control, to program particular logic functions the circuit will perform. When an integrated circuit manufacturer supplies a typical programmable logic device, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, can program the PLD to perform a particular function or functions required by the user's application. The PLD then can function in a larger system designed by the user just as though dedicated logic chips were employed.
As used herein PLDs include complex PLDs (“CPLDs”), programmable array logic (“PALs”), programmable logic arrays (“PLAs”), field PLAs (“FPLAs”), erasable PLDs (“EPLDs”), electrically erasable PLDs (“EEPLDs”), logic cell arrays (“LCAs”), field programmable gate arrays (“FPGAs”).
In addition to the general purpose circuitry typically included in the architecture of a PLD, PLDs may also include various types of special-purpose circuitry, referred to as functional blocks. Examples of such special-purpose circuitry are microprocessor circuitry, digital signal processing (DSP) circuitry, memory blocks, etc.
Because PLDs are typically designed to satisfy any of a wide range of needs, it may also be desirable for any special-purpose circuitry that is included to also have some flexibility with regard to the functions it can perform. For example, in the case of a user non-volatile memory block, it may be desirable to provide multiple interface protocols and allow the user to select the desired protocol. Additionally, it may be desirable to have such flexibility while minimizing the circuitry needed to provide the multiple interface protocols.